There is a desire to fabricate an image sensor in a thin-film polysilicon process which is compatible with that used in the manufacture of thin-film transistor substrates for active matrix liquid crystal displays (AMLCDs). By using such a fabrication process, such an image sensor may be monolithically integrated within an AMLCD in order to provide, for example, an input function for detecting a touch or pen input. In such an arrangement, each pixel may include both image sensing and displaying elements to provide similar spatial resolutions of image sensing and display. However, the presence of the image sensing function within the pixels reduces the aperture ratio of such a display as compared with a display in which no image sensing function is provided.
Several types of semiconductor image sensors exist, including those based on charge-coupled device (CCD) technology and those based on complementary metal oxide silicon (CMOS) technology. CCDs have historically offered higher quality performance than CMOS image sensors because of the specialized process technologies for maximizing the transfer efficiency of photo-generated charges. However, CMOS image sensors have an advantage in that both an imaging array and signal processing electronics may be integrated onto the same chip whereas the specialized nature of CCD processes prohibits such integration. CMOS image sensors therefore have advantages of lower cost for many applications, for example in consumer electronics.
Two main types of CMOS image sensors are known, namely passive pixel sensors (PPS) and active pixel sensors (APS). Passive pixel sensors include a photodiode or similar photo sensitive device and a “select” transistor within each pixel of the image sensor. An image sensor array is addressed by row and the current generated by each photodiode is integrated for the duration of one row period by an integrator located typically at the bottom of each column. Because each pixel contains only two active devices, passive pixel arrangements permit a high resolution array to be provided. However, the size of such an array is limited by the time needed to integrate each row sequentially and the output signals suffer from a relatively large degree of noise associated with fluctuations in the column current during integration.
APS devices include an amplifier in each pixel and so do not suffer from the limitations of PPS arrangements. FIG. 1 of the accompanying drawings illustrates an example of an APS with a photogate-based pixel circuit, for example as disclosed in U.S. Pat. No. 5,471,515. In operation, during an integration period, electrons accumulate in a potential well beneath a photogate 30 in proportion to a photon flux incident on a substrate beneath the photogate electrode. At the end of each integration period, the potential of a floating diffusion region 40 is reset to an initial level by applying a resetting signal pulse RST. The charge accumulated on the photogate is then transferred to the floating diffusion region 40 during a transfer step controlled by a pulse TX. The potential of the floating diffusion region 40 is thus indicative of the charge accumulated during the integration period.
When a row of pixels is sampled, a row select transistor 60 is turned on by a row scan pulse (ROW). A transistor 55 is connected as a source-follower cooperating with a bias transistor 65 disposed at the end of a column of the pixel array. The gate of the transistor 55 is connected to a floating diffusion node so that the output of the source-follower provides an indication of the voltage at the gate of the transistor 55 and hence of the charge accumulated in the pixel during the integration period.
The image sensor chip also comprises circuitry for reading out the sampled pixel signal as illustrated at 70 in FIG. 1. When the row containing the sensing element is selected, the source follower output voltage representing the incident light intensity is stored in a capacitor 205 via a transistor 200. Transistors 210, 215 and 220 form another source-follower for the column containing the sensing element. When the column select signal COL is pulsed, the output of the column source-follower is supplied to a chip amplifier via an output OUT. The column source-followers are enabled in turn so that the image sensor output voltage is a time-sequential representation of the light intensity incident on each pixel of the array.
The arrangement shown in FIG. 1 also comprises devices 116, 225, 230, 235, 240 and 245 which are used to generate a reference voltage for the chip amplifier for reducing offset errors. The operation of such an arrangement is known and will not be described further.
FIG. 2 of the accompanying drawings illustrates a sensor element of the APS type including a photodiode 1 of the “bulk” or vertical type, for example as disclosed in “128×128 CMOS photodiode-type active pixel sensor with on-chip timing, control, and signal chain electronics”, E Fossum et al, Charge-Coupled Devices and Solid-State Optical Sensors V, Proc. SPIE, Vol 2415, pp 117-123, 1995. The sensing element comprises a resetting transistor 2 connected between a supply line VDD and the cathode 3 of the photodiode 1. The gate of the transistor 2 receives a reset signal RST and reverse-biases the photodiode 1 so as to charge its capacitance to a predetermined voltage. The reset phase is followed by a sensing phase during which integration is performed whereby the photodiode current discharges its capacitance at a rate proportional to the photon flux incident on the photodiode 1. A transistor 4 is connected as a source-follower with its source-drain or “main conduction” path connected in series with that of a selecting transistor 5 between the supply line VDD and a column buss COL BUS of a sensing element array. When a row of pixels is sampled, the row select transistor 5 is turned on by a pulse RS. The column bus is connected to a column reading arrangement, for example of the type illustrated by the transistor 65 and the circuit 70 in FIG. 1, to allow the output voltages from the row of pixels to be read out of the sensor.
US 2006/0033729 A1 discloses a device comprising an image sensor integrated within an AMLCD as illustrated in FIG. 3 of the accompanying drawings. Each pixel comprises a display portion and an image sensing portion with the latter being of a type similar to that shown in FIG. 2 of the accompanying drawings. In this device, each photodiode comprises a thin-film photodiode fabricated using the same process technology as used for manufacture of the AMLCD thin-film transistor (TFT) substrate. A separate integration capacitor is required in this case because the ratio of the photocurrent to self-capacitance of the thin-film photodiode is large compared to that for a bulk CMOS device. Thus, in the absence of the integration capacitance, the pixel discharge rate would be too high for practical use.
Such a device may be operated in shadow mode or reflection mode. In shadow mode, objects above the AMLCD block the path of ambient light and cast a shadow on the surface of the display, which shadow is detected by the image sensor array. This mode may be used, for example, for touch, pen or gesture input. In reflection mode as illustrated in FIG. 4 of the accompanying drawings, light from a display backlight 23 passes through a counter-substrate 24, a liquid crystal layer 25 and a TFT substrate 21 so as to be incident on an object 22 in front of the device. Light reflected from the object 22 returns to the image sensor array for conversion into a corresponding signal. Examples of applications for the reflection mode include contact-type image scanning and fingerprint recognition and identification.